AN ULTRA-LOW-POWER AND ADAPTIVE APPROXIMATE MULTIPLIER

Volume no :

2 |

Issue no :

1

Article Type :

Scholarly Article

Author :

G.Rajarajeshwari, B.Angel Paulina, B.Dhivya Dharshini, R.Lisha

Published Date :

May, 2025

Publisher :

INTERNATIONAL JOURNAL OF ENGINEERING INNOVATIONS AND MANAGEMENT STRATEGIES

Page No: 1 - 10

Abstract : This article provides the design and implementation of high-speed 32x32 and 64x64 binary arithmetic multipliers using Adaptive Approximate mathematics, particularly based on the 'Urdhava Tiryagbhyam' sutra for partial product formation. The Adaptive Approximate multiplication scheme reduces the multiplication process by breaking down the process into fewer steps, which reduces the overall latency significantly compared to existing methods. The partial product addition is dealt efficiently using the use of a Brent-Kung adder, a fast parallel prefix adder used for its high speed and low carry propagation delay to perform the addition efficiently for multiplications involving large bits. The HDL design is coded using Verilog and then synthesized using Xilinx ISE 14.7 software. The performance of the proposed 32x32 and 64x64 Adaptive Approximate multipliers is compared and analyzed with traditional multipliers based on MUX based adders. The analysis indicates that the proposed Adaptive Approximate multiplier coupled with the use of a Brent-Kung adder provides better performance using low combinational path delay and high throughput for large-bit multiplications. This method offers an efficient high-speed arithmetic methodology for use in VLSI systems.

Keyword Area, Power Consumption, Delay, Brent Kung adder

Reference:

Kumar, S., Sharma, R. K., & Gupta, S. (2022). High-Speed Adaptive Approximate Multiplier Design Using Parallel Prefix Adder. IEEE Transactions on Circuits and Systems II: Express Briefs, 69(5), 2043-2047.
Agarwal, N. K., Sharma, R., & Tiwari, R. (2022). FPGA-Based Optimized Approximate Multiplier for Digital Signal Processing Applications. Journal of Low Power Electronics and Applications, 12(3), 23.
Meena, P. S., & Tripathi, R. C. (2022). Use of Brent-Kung Adder in Adaptive Approximate Multiplier Design to Reduce Power Consumption and Increase Speed. IEEE Access, 10, 11234-11245.
Gupta, R., & Garg, S. K. (2022). Design and Implementation of an Adaptive Approximate Multiplier. IET Digital Signal Processing, 16(2), 238-244.
Singh, M., Sahu, P. K., & Gupta, P. K. (2023). High-Speed 64×64-Bit Adaptive Approximate Multiplier Using FPGA. Microprocessors and Microsystems, 78, 103450.
Kahng, A. B., & Robins, D. (2000). Dynamic Power Management in VLSI Systems. Springer Science & Business Media.
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Murphy, R., & Murphy, A. (2022). FPGA Implementation of Approximate Multiplier Designs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 30(9), 1221-1230.

Abstract

This paper presents the design and implementation of high-speed 32×32 and 64×64 binary arithmetic multipliers using adaptive approximate arithmetic. The proposed method is based on the ancient Vedic math technique, “Urdhva Tiryagbhyam,” for efficient partial product formation. It reduces the multiplication process into fewer steps, significantly lowering latency. A Brent-Kung adder, a high-speed parallel prefix adder, handles the partial product addition with minimal carry propagation delay.ULTRALOWPOWER ADAPTIVE MULTIPLIER

We coded the hardware design in Verilog and synthesized it using Xilinx ISE 14.7. The performance of the proposed multipliers was compared with traditional MUX-based multipliers. Our results show that the adaptive approximate method, combined with the Brent-Kung adder, achieves higher speed and lower combinational delay. This solution proves ideal for large-bit arithmetic operations in modern VLSI systems.

AN ULTRA-LOW-POWER AND ADAPTIVE APPROXIMATE MULTIPLIER

Introduction

In Very-Large Scale Integration (VLSI) design, arithmetic operations greatly influence system speed, energy efficiency, and functionality. Among these, multiplication is the most crucial yet computationally demanding function. It is essential in fields like signal processing, cryptography, and real-time data handling. However, multiplying large bit-width values increases complexity, time, and resource usage.ULTRALOWPOWER ADAPTIVE MULTIPLIER

Conventional multipliers such as array and Booth multipliers are simple to design but struggle with speed and area efficiency for larger inputs. Their main limitation lies in partial product generation and summation delays.To address this To address this

To address this, engineers have explored adaptive approximate techniques that trade precision for speed while maintaining acceptable accuracy. One promising method is based on the Vedic multiplication technique, especially the “Urdhva Tiryagbhyam” sutra. This vertical and crosswise approach generates partial products more efficiently and simplifies the computation.

This study uses that approach along with Brent-Kung adders to build 32×32 and 64×64 multipliers that outperform traditional designs. The goal is to achieve faster, low-latency arithmetic suited for high-performance digital systems.